The fabrication of semiconductor integrated circuits, or chips as they are commonly known, is an extremely complex process that involves several hundred or more operations. They are fabricated by selectively implanting impurities into, and applying conductive and insulative layers onto, a semiconductor substrate. Semiconductor chips are not manufactured individually, but rather as an assembly of a hundred or more chips on a "wafer," which is then diced up to produce the individual chips.
An ongoing problem in the manufacture of semiconductor chips has to do with yield. Because of various defects that can occur in fabrication of a wafer, significant numbers of wafer die have to be discarded for one reason or another, thereby decreasing the percentage yield per wafer and driving up the cost of individual chips. Defects are typically caused by foreign particles, minute scratches and other imperfections introduced during photoresist, photomask and diffusion operations. Yield impacts the number of wafer starts at the inception of production needed to meet specific customer order quantities for finished chips at the end of the production line. With the high demand for semiconductor chips and more orders than can possibly be filled by a fabrication facility, predicting yield to accurately gauge wafer starts, and utilizing defect data to remove yield detracting operations, are important aspects of improving the efficiency, and hence output, of the fabrication facility.
Wafer scanning tools are utilized to identify deflects that occur in the chip manufacturing process for the aforementioned purposes. Typically, such tools are located at a variety of positions along the production line and comprise automated-vision inspection stations for identifying visual irregularities in the wafer die as they move through the line. The irregularities, i.e., defects, are recorded according to their coordinates, estimate of size or other parameters and are stored as records in a database. The records represent raw information that must then be analyzed or otherwise processed off line to determine the impact, if any, of the identified defects on product yield. Some defects, for example, do not adversely affect yield as much as others, and therefore must be classified differently for analysis purposes.
Commercially available wafer scanning tools include those made by KLA Instruments Corporation of Santa Clara, Calif., Tencor Instruments Corporation of Mountain View, Calif., Inspex, Inc. of Billerica, Mass. and numerous other manufacturers. Despite significant advances made in wafer scanning technology, the various tools that are available suffer striking deficiencies. In particular, such tools lack the capability to perform advanced classification and analysis of defect information necessary to accurately determine the true impact of wafer defects on yield. While conventional tools offer simple data presentation capabilities, such as the display of wafer maps, histograms and charts, they do not adequately classify or process the defect data. Classification codes must typically be manually entered into wafer scan records indicating the type of defect and its potential impact on yield. This is done by placing the wafer on a review station where a user makes a judgment as to what the defect identified by the scan toot is, enters a classification code in the record for that defect, then proceeds to the next defect.
More sophisticated tools perform limited automatic classification of defect records according to the location of the defect on the wafer, in an effort to remove consideration of defects that do not require any classification. For example, it is recognized that a number of defect points in close proximity to one another, collectively referred to as a "cluster," can indicate a single event such as a contaminant or scratch present across one or more die. In this day and age of increased automation and reduction of manual operations and procedures in semiconductor processing, scratches continue to be a concern as a source of die loss in processing. This form of die loss is of special interest because scratches are considered an "avoidable" defect; however, the recognition of a scratch problem and the subsequent tracking down of the cause of such a problem can be anything but simple.
Scratches are caused by mechanical contact on the wafer's surface during processing. Such defects are caused by either a misalignment of a robotics handling system or sloppy and/or careless handling by manufacturing personnel. Defect detection tools can reveal scratch "patterns" on wafers when the full wafer map is displayed. Obviously, manual identification of scratches using defect maps is a fairly uncomplicated process; however, when one considers that hundreds of wafers per inspection tool are scanned per day, it is apparent that the time required to review each map individually to determine whether scratches are present can be an overwhelming task.
Consequently, there is a need for a method and system that permits more accurate defect analysis to be performed in cooperation with semiconductor wafer scanning tools and, particularly, a method and system that automatically recognizes scratch patterns on scanned semiconductor wafers.